.. _Tools:

Tools
#####

Installed via submodules
========================

* `third_party/netlistsvg <https://github.com/nturley/netlistsvg/>`__
  Tool for generating nice logic diagrams from Verilog code.

* `third_party/icestorm <https://github.com/cliffordwolf/icestorm/>`__
  Bitstream and timing database + tools for the Lattice iCE40.

* `third_party/prjxray <https://github.com/f4pga/prjxray/>`__
  Tools for the Xilinx Series 7 parts.

* `third_party/prjxray-db <https://github.com/f4pga/prjxray-db/>`__
  Bitstream and timing database for the Xilinx Series 7 parts.

Installed via conda
===================

* `yosys <https://github.com/YosysHQ/yosys>`__
  Verilog parsing and synthesis.

* `vtr <https://github.com/verilog-to-routing/vtr-verilog-to-routing>`__
  Place and route tool.

* `iverilog <https://github.com/steveicarus/iverilog>`__
  Very correct FOSS Verilog Simulator

Potentially used in the future
==============================

* `verilator <https://www.veripool.org/wiki/verilator>`__
  Fast FOSS Verilog Simulator

* `sphinx <http://www.sphinx-doc.org/en/master/>`__
  Tool for generating nice looking documentation.

* `breathe <https://breathe.readthedocs.io/en/latest/>`__
  Tool for allowing Doxygen and Sphinx integration.

* ``doxygen-verilog``
  Allows using Doxygen style comments inside Verilog files.

* `symbolator <https://kevinpt.github.io/symbolator/>`__
  Tool for generating symbol diagrams from Verilog (and VHDL) code.

* `wavedrom <https://wavedrom.com/>`__
  Tool for generating waveform / timing diagrams.