Important

Since May 2022, packages providing Architecture Definition assets do not include CLI utilities/wrappers to interact with Yosys, Verilog-to-Routing, etc. For backwards compatibility, end-users can install Python package f4pga from gh:chipsalliance/f4pga. For instance: pip install https://github.com/chipsalliance/f4pga/archive/main.zip#subdirectory=f4pga.

Tools

Installed via submodules

• third_party/netlistsvg Tool for generating nice logic diagrams from Verilog code.

• third_party/icestorm Bitstream and timing database + tools for the Lattice iCE40.

• third_party/prjxray Tools for the Xilinx Series 7 parts.

• third_party/prjxray-db Bitstream and timing database for the Xilinx Series 7 parts.

Installed via conda

• yosys Verilog parsing and synthesis.

• vtr Place and route tool.

• iverilog Very correct FOSS Verilog Simulator

Potentially used in the future

• verilator Fast FOSS Verilog Simulator

• sphinx Tool for generating nice looking documentation.

• breathe Tool for allowing Doxygen and Sphinx integration.

• doxygen-verilog Allows using Doxygen style comments inside Verilog files.

• symbolator Tool for generating symbol diagrams from Verilog (and VHDL) code.

• wavedrom Tool for generating waveform / timing diagrams.