Minitests for ISERDES+IDELAY

1. basys3_iserdes_idelay_histogram

This design transmitts a pseudo-random data stream throught one output pin and then receives it through another one with the use of IDELAY and ISERDES. A physical loopback is required. The received data is serialized again (internally) and the received bitstream compared with the transmitted one. This is agnostic to ISERDES configuration. Receive errors are counted separately for each one of 32 possible delay settings of the IDELAY bel. Values of 32 error counters are periodically pinted using the UART as an ASCII string.

There is a control state machine which performs the following sequence once per ~0.5s (adjustable).

  1. Set delay of the IDELAY bel.

  2. Wait for it to stabilize (a few clock cycles)

  3. Compare received and transmitted data and count errors. Do it for some period of time (adjustable).

  4. Repeat steps 1-4 for all 32 delay steps

  5. Output error counters through the UART

  6. Wait

The physical loopback has to be connected between JXADC.7 and JXADC.8 pins.

Consider the JXADC connector on the Basys3 board as seen when looking at the board edge:

 -- -- -- -- -- --
| 6| 5| 4| 3| 2| 1|
 -- -- -- -- -- --
|12|11|10| 9| 8| 7|
 -- -- -- -- -- --
  • Pin1 - Received signal output, through IDELAY and ISERDES.O (for reference)

  • Pin2 - Transmitted signal output (for reference).

  • Pin3 - Serialized data clock that the ISERDES operates on (for reference)

  • Pin7 - Physical loopback input, connect to Pin8

  • Pin8 - Physical loopback output, connect to Pin7

Important: Make the connection between Pin7 and Pin8 no longer than ~10cm (~4inch). You can use cables of different length to see how it affects the signal delay.

Example UART output:


There are 32 hex numbers separated by “_”. Each one correspond to one error counter.

An utility script iserdes_idelay_histogram_receiver.p can be found in the utils subdirectory. It reads and parses data received through UART and prints counter values in decimal.