Project X-RayΒΆ
Project X-Ray documents the Xilinx 7-Series FPGA architecture to enable development of open-source tools. Our goal is to provide sufficient information to develop a free and open Verilog to bitstream toolchain for these devices.
Introduction
Getting Started
Xilinx 7-Series Architecture
Database Development Process
- Project X-Ray
- Quickstart Guide
- C++ Development
- Process
- Database
- Current Focus
- Contributing
- Contributing to Project X-Ray
- Adding New Fuzzer
- Fuzzers
- Minitests
- CLB_BUSED Minitest
- CLB_MUXF8 Minitest
- FIXEDPNR Minitest
- Display Port minitest
- Minitests for IDELAY
- Minitests for ISERDES+IDELAY
- ISERDES minitest for SDR and DDR
- LiteX minitest
- LiteX Litex BaseSoC + LiteDRAM minitest
- Minitest for OSERDES
- FASM Proof of Concept using Vivado Partial Reconfig flow
- PICORV32-v Minitest
- PICORV32-y Minitest
- PLLE2_ADV minitest
- ROI_HARNESS Minitest
- Minitests for SRLs
- Timing minitest
- Zynq7 EMIO minitest
- Building & loading
- Tools
- Guide to adding a new device to an existing family
Output Formats