This test verifies operation of the
PLLE2_ADV primitive. The PLL is configured to output clocks using the following dividers:
The input clock can be swtched between 100MHz and 50MHz using the
sw switch. The 50MHz clock is generated using simple divider implemented in logic.
Clocks from the PLL are further divided by 2^21 and then fed to LEDs 0:5. PLL lock indicator is connected to LED 15. The switch
sw provides reset signal to the PLL.
To build the project run the following command and the bit file will be generated.